Please use this identifier to cite or link to this item: http://148.72.244.84:8080/xmlui/handle/xmlui/10433
Full metadata record
DC FieldValueLanguage
dc.contributor.authorSafana Hyder Abbas, Salam Ayad Hussein-
dc.date.accessioned2023-11-30T08:38:55Z-
dc.date.available2023-11-30T08:38:55Z-
dc.date.issued2012-07-01-
dc.identifier.issn2222-8373-
dc.identifier.urihttp://148.72.244.84:8080/xmlui/handle/xmlui/10433-
dc.description.abstractCaching is a fundamental technique commonly employed to hide the latency gap between memory and the CPU by exploiting locality in memory accesses. Different cache replacement algorithms have dramatically different effects on the system performance by deciding which blocks to evict from cache memory in case of a cache miss occurs. The aim of these replacement techniques is trying to get closer to the optimal case by achieving best usage of the total size of the cache, minimizing the miss ratio as much as possible and accomplishing the highest system performance can be reached. In this paper, a simple and elegant new algorithm is proposed, namely, Two-Dimensional Pyramid Replacement, (2-DPR), that combines the advantages of (LRU) and (LFU), and eliminates their disadvantages.en_US
dc.description.sponsorshiphttps://djps.uodiyala.edu.iq/uploads/Volume%2012/Issue%203/Part%202/English/98-113%20E.pdfen_US
dc.language.isoenen_US
dc.publisheruniversity of Diyalaen_US
dc.subjectCache Memory, Replacement Algorithms, Cache Miss, Cache Hit.en_US
dc.title2-DPR: A Novel, High Performance Cache Replacement Algorithmen_US
dc.typeArticleen_US
Appears in Collections:مجلة ديالى للعلوم الاكاديمية / Academic Science Journal (Acad. Sci. J.)

Files in This Item:
File Description SizeFormat 
98-113 E.pdf648.63 kBAdobe PDFView/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.